• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    An integrated circuit (IC) comprising a substrate (1), at least a first domain (D1), and at least a second domain (D2) distinct from said at least one first domain (D1), wherein the substrate (1) contains a trap-rich region (CP) only in said at least one second domain (D2).
    公开号:FR3078436A1
    申请号:FR1851615
    申请日:2018-02-23
    公开日:2019-08-30
    发明作者:Didier Dutartre
    申请人:STMicroelectronics Crolles 2 SAS；
    IPC主号:
    专利说明:

    Integrated circuit comprising a substrate equipped with a region rich in traps, and manufacturing method
    The invention relates to the field of electronics and more specifically that of semiconductor substrates allowing the production of electronic circuits, in particular dedicated to radiofrequency applications.
    In particular, embodiments and embodiments of the invention relate to substrates of the silicon on insulator type, also called “SOI” substrate in English for “Silicon On Insulator” dedicated to radiofrequency applications and very particularly substrates completely deserted silicon type on FD-SOI insulator (from the English "Fully Depleted Silicon On Insulator").
    An SOI type substrate conventionally comprises a semiconductor film (or upper semiconductor layer) located above a buried insulating layer (silicon oxide in general), commonly known by the acronym BOX (after l 'English "Burried OXide"), itself located above a carrier substrate, for example a solid substrate.
    Radiofrequency (RF) integrated circuits are generally preferably manufactured on P-doped semiconductor substrates of the so-called “HR” type, that is to say of high resistivity (typically greater than 1 kOhm.cm), so as to limit losses in the substrate and crosstalk (“cross-talk”) between neighboring components, by conduction.
    It is also common to use HR substrates of the SOI (Silicon On Insulator) type. The passive or active components formed in and on the semiconductor film are then isolated from the carrier substrate by the buried oxide layer.
    However, it has been observed that using such substrates reduces the losses linked to the substrate without completely eliminating them. Indeed, fixed electrical charges are inevitably present in the buried insulating layer (BOX) due to the manufacturing process of this oxide layer. They are responsible for the accumulation in the substrate, in the vicinity of the BOX, of mobile electrical charges which can form a conductive channel. Thus, although HR type substrates are used, the parasitic surface conduction in the substrate is the source of electrical losses.
    The semiconductor film / BOX / carrier substrate stack also behaves like a MOS (Metal Oxide Semiconductor) capacity. As a first approximation, we consider that the thickness of the inversion layer associated with this MOS capacity changes inversely with the square root of the dopant concentration of the carrier substrate. It can therefore be seen that this thickness is all the more important since the carrier substrate is of the HR type, that is to say with low doping. This capacity has the characteristic of being modulated by the electrical potential applied to the components formed in or on the insulated silicon film, opposite and above the BOX. This modulated stray capacitance is responsible for harmonic distortions and crosstalk affecting the RF components of integrated circuits, in a manner detrimental to the performance of these components. Such a distortion can in particular be quantified by the method of determining the third order interception point, or in English "Third order intercept point", abbreviated as TOIP or IP3.
    In order to remedy this phenomenon, it is known to use more complex carrier substrate structures, integrating a specific region separating the monocrystalline part of the carrier substrate and the buried insulating layer (BOX) so as to create, near this one. ci, a high density of surface states likely to trap free carriers. This trapping of free carriers by the surface states greatly reduces the parasitic surface conduction phenomenon. It also causes the Fermi level to be anchored in the semiconductor, at the carrier-BOX interface (“Fermi level pinning”), which makes the value of the parasitic MOS capacity largely independent of the electrical potential applied to the components. formed opposite, above the buried insulating layer (BOX), thus limiting harmonic distortions. Such specific regions are known to those skilled in the art under the term Anglo-Saxon "trap-rich" regions (regions rich in traps). Such a substrate is called a "trap-rich" substrate.
    The “trap-rich” regions and their creation have been the subject of numerous publications, including the document “SOI technology: An Opportunity for RF Designers, Journal of 30 Telecommunications and Information Technology, 04/2009” or even international patent application PCT / EP2015 / 056719, which describe an embodiment of a region rich in “trap-rich” charge traps under the buried insulating layer (BOX) of an SOI substrate.
    However, the production of an integrated circuit in and on the semiconductor film comprises steps of annealing at high temperature, typically well above 1000 ° C., in particular for forming shallow insulating trenches "STI in English for Shallow Trench Isolation ”. However, such annealing results in the creation of a roughness at the level of the upper surface of the region rich in traps which results in a roughness of the semiconductor film, which is detrimental to the proper functioning of certain components of the integrated circuit.
    The placement of the “trap-rich” region under the insulating layer buried in an SOI type substrate is all the more problematic as the FD-SOI type substrate because the thickness of the semiconductor film is particularly low. , typically a few nanometers. Likewise, the thickness of the buried insulating layer (BOX) is low, typically of the order of 15 to 25 nm.
    There is therefore a need to propose, according to one embodiment, an SOI type substrate, in particular FD-SOI, and the presence of a region rich in traps (“trap-rich”) is not detrimental to the surface condition of the semiconductor film of such a substrate.
    According to one aspect, an integrated circuit is proposed comprising a substrate, at least a first domain, and at least a second domain distinct from said at least first domain, in which the substrate contains a region rich in traps only in said at least one second. field.
    Thus, unlike the prior art, the production of a "trap-rich" region is localized only at certain locations on the substrate.
    According to one embodiment, said at least one first domain contains at least one non-radio frequency component and said at least one second domain contains at least one radio frequency component.
    A radiofrequency component is a component capable of being coupled to (for example crossed by) at least one radiofrequency signal during the operation of the integrated circuit. Such a component is for example but not limited to a passive component of the inductance, capacitor, resistance type, or even a waveguide.
    A non-radio frequency component is a component different from a radio frequency component, typically a component not intended to be coupled to a radio frequency signal, for example a transistor belonging to a logic part of the integrated circuit.
    According to one embodiment, the substrate is of the silicon on insulator type comprising in said at least one first domain, a semiconductor film, a first part of a carrier substrate and a buried insulating layer located between said first part of the carrier substrate and the semiconductor film, and comprising in said second domain a second part of the carrier substrate surmounted by said region rich in traps, the semiconductor film and said buried insulating layer not extending in said at least one second domain.
    According to one embodiment, the substrate is of the totally deserted silicon on insulator type, the semiconductor film comprising a totally deserted semiconductor material.
    The region rich in “trap-rich” traps is therefore present only in a field comprising radiofrequency components. This presence is advantageous because it makes it possible to limit the harmonic distortions and the crosstalk affecting the radiofrequency components of said domain of the integrated circuit.
    And this presence does not affect the surface roughness of the semiconductor film of an SOI type substrate, in particular of FDSOI type, because in the second domain (radio frequency) the semiconductor film is not present. And the roughness of the semiconductor film of an SOI substrate, in particular FD-SOI, is not impacted in the first domain (non-radio frequency domain) by the region rich in traps which is absent, this absence does not harm the correct functioning of the non-radio frequency components.
    A region rich in traps (“trap-rich”) is a region whose name (“rich in traps”) and structure are well known to those skilled in the art, given the numerous publications existing on this subject.
    However, we can also define, by way of nonlimiting example, a region rich in traps as being a region which when it is located under a radiofrequency component crossed by a radiofrequency signal, leads to attenuation of at least 85 dBm of the second harmonic of this signal.
    According to one embodiment, said region rich in traps comprises at least one stack comprising a layer of polycrystalline semiconductor material, and an interface zone located between an underlying part of the substrate and the layer of polycrystalline semiconductor material, said interface zone having a structure distinct from the crystal structure of said layer of polycrystalline semiconductor material, and from the crystal structure of the underlying part of the substrate.
    According to one embodiment, said at least one layer of polycrystalline semiconductor material has a thickness of between 0.5 and 3 μm.
    According to one embodiment, when the substrate is of the SOI type, the underlying part of the substrate is said second part of the carrier substrate.
    According to one embodiment, the carrier substrate comprises a high resistivity substrate.
    A high resistivity substrate is a low doping substrate, and which typically has a resistivity greater than 1 kOhm.cm.
    This type of substrate is particularly appreciated for the production of radiofrequency components because it limits losses in the substrate and crosstalk (“cross-talk”) between neighboring components, by conduction.
    According to another aspect, there is also proposed a method for producing an integrated circuit comprising producing a region rich in traps in only a first part of a substrate of the integrated circuit.
    According to one embodiment, the method comprises an embodiment of a first domain containing at least one non-radio frequency component and an embodiment of a second domain containing at least one radio frequency component as well as the region rich in traps.
    According to one embodiment, the method comprises producing isolation zones in the substrate, carried out after the production of said region rich in traps.
    According to one embodiment, the substrate is of the silicon on insulator substrate type comprising a semiconductor film, a carrier substrate and a buried insulating layer located between the carrier substrate and the conductive film, and the production of the region rich in traps includes:
    - An embodiment of a trench in said at least one second area extending into the carrier substrate;
    - A formation of at least one interface zone on the internal wall of said trench, said interface zone having a crystal structure different from the carrier substrate;
    a formation of at least one layer of polycrystalline semiconductor material on said at least one interface zone, the layer of polycrystalline semiconductor material forming said region rich in traps, having an upper surface located substantially in the same plane as the upper surface of the semiconductor film, and having a structure distinct from the crystal structure of the interface region.
    A surface located substantially in the same plane as another surface means located in the same plane except for a tolerance, this tolerance being linked to the characteristics of the technological processes used to obtain these surfaces.
    According to one embodiment, the substrate is of the totally deserted silicon on insulator type, the semiconductor film comprising a totally deserted semiconductor material.
    According to one embodiment, the carrier substrate is a high resistivity substrate.
    Other advantages and characteristics of the invention will appear on examining the detailed description of modes of implementation and embodiments, in no way limiting, and the appended drawings in which:
    - Figures 1 to 6 schematically illustrate an embodiment of a method according to the invention and an embodiment of an integrated circuit according to the invention.
    Of course, to facilitate understanding, the different elements shown in the figures, and in particular the layers making up the silicon-on-insulator type substrate, have been shown diagrammatically, and the proportions of these different elements may deviate from the actual proportions.
    FIG. 1 represents a sectional view of a substrate of silicon on insulator type also called “SOI” substrate in English for “Silicon On Insulator”.
    The SOI type substrate conventionally comprises a semiconductor film 30 situated above a buried insulating layer 20 (of silicon oxide in general), commonly designated by the acronym BOX (from the English Burried OXide), itself located above a carrier substrate 10.
    In this example, the substrate is in particular of the FD-SOI type, although the invention can be applied to any type of SOI substrate.
    For a FD-SOI type substrate, the material forming the semiconductor film, typically silicon, is completely deserted. In this regard, the material has an intrinsic doping, typically of the order of 10 15 atoms of dopants per cm 3 . The thickness of the semiconductor film 30 can be between 5 and 6 nm, and the thickness of the insulating layer 20 can be approximately 25 nm.
    The carrier substrate 10 can be made from any semiconductor material, and in particular based on monocrystalline silicon.
    The carrier substrate here is advantageously a semiconductor substrate with high resistivity, that is to say with relatively low doping, and typically has a resistivity greater than 1 kOhm.cm. This type of substrate is particularly appreciated for the production of radiofrequency components.
    Of course, this does not exclude the possibility of using another type of non-high resistivity substrate.
    In FIG. 2, a layer 40 known as a “hard mask” (from the English “Hard Mask”) is deposited on the upper face of the semiconductor film 30. This layer aims in particular to protect the semiconductor film 30 and will also serve, as will be seen below, as an etching mask.
    This layer 40 can, for example, be made of silicon nitride, oxide-nitride-oxide (ONO) or any other suitable material.
    A resin layer 50 of photosensitive material is deposited on the upper face of the hard mask layer 40.
    As illustrated in FIG. 3, the integrated circuit which will be produced in and on the substrate 1, comprises several areas.
    More specifically, a first domain DI is intended to receive non-radiofrequency components while a second domain D2 is intended to receive radiofrequency components.
    Of course, each area can be made up of a single area or of several separate areas.
    As illustrated in FIG. 3, a conventional photolithography, exposure and development of the resin layer 50 step is carried out to delimit the domain D2, then using the residue of resin as an etching mask, to a conventional GR1 etching and known per se from the hard mask layer 40.
    The upper surface of the buried insulating layer located above the part 12 of the carrier substrate is then uncovered.
    The resin layer 50 is then removed.
    As illustrated in FIG. 4, conventional etching operations GR2 are known and known per se, to form a trench TR extending into part 12 of the carrier substrate 10.
    The trench TR has a depth of, for example, between 0.5 and 2 µm.
    This TR trench represents the future location of a region rich in traps known by the skilled person under the term Anglo-Saxon region "trap-rich".
    Thus, this region rich in traps will be located only in the domain D2 which will advantageously include radio frequency components.
    This presence is advantageous because it makes it possible to limit the harmonic distortions and the crosstalk affecting the radiofrequency components of the domain D2 of the substrate 1.
    This presence does not affect the surface roughness of the semiconductor film 30 of the domain D2 of the substrate 1 of FD-SOI type, because in the domain D2 (radiofrequency), the semiconductor film 30 is not present.
    On the other hand, the semiconductor film 30 being present in the DI domain of the substrate 1, its roughness is not impacted by the region rich in traps which is absent therefrom, this absence not affecting the proper functioning of the non-radio frequency components.
    As illustrated in FIG. 5, a layer 60 of polycrystalline semiconductor material is deposited on the upper face of the hard mask layer 40 and on the wall of the trench TR, so as to fill the trench and form a rich region CP in traps.
    To avoid epitaxial growth of the layer 60 of polycrystalline semiconductor material on the underlying monocrystalline carrier substrate 12, it is advisable to form an interface zone ZI on the internal wall of the trench TR before depositing the layer 60 of polycrystalline semiconductor material. This allows the formation of the layer of polycrystalline semiconductor material without epitaxial recovery and therefore, the formation of traps leading to the formation of the region rich in traps.
    Different techniques can be used to form the ZI interface area. It is thus possible to expose the wall of the trench TR to an environment comprising oxidizing species.
    Oxidation phenomena create in the internal wall of the trench TR a layer ZI of very thin thickness of the order of magnitude of the nanometer, which has a structure distinct from the crystal structure of the grains of the polycrystalline semiconductor material 60 and of the underlying monocrystalline carrier substrate 12.
    This oxidation can be carried out by a controlled thermal oxidation of the RTO type (from the English "Rapid Thermal Oxidation"), that is to say an oxidation whose kinetics is increased by heating the internal wall TR, typically between 550 ° C and 900 ° C, in the presence of an oxidizing atmosphere.
    It is also possible to carry out this oxidation by carrying out an oxidizing treatment of wet chemistry according to conventional procedures.
    Among the other possibilities for producing the interface zone ZI, mention may be made of ion implantation operations of non-doping species, such as argon, germanium or any other heavy ion. Such ion bombardment makes it possible to create a large number of crystalline defects or to amorphize, at least partially, the internal wall of the TR trench, that is to say to break the crystalline arrangement on the surface of the grains, this which avoids epitaxial growth during the deposition of the layer of polycrystalline semiconductor material 60.
    Thus, once the interface layer ZI has been produced, the layer 60 of polycrystalline semiconductor material can be deposited in the trench TR and on the hard mask layer 40.
    The deposition of the layer of polycrystalline semiconductor material CP can be done by a chemical vapor deposition technique, so as to form a layer whose thickness is preferably between 500 nanometers and 2000 nanometers or even more, for example 3000 nanometers.
    Optionally, after its deposition, the layer of polycrystalline semiconductor material 60 can undergo a heat treatment adapted to its thickness and to its nature, so as to stabilize its structure by recrystallizing it.
    Of course, other deposition techniques can be used to form this layer, for example low pressure chemical vapor deposition (LPCVD), or more generally by any type of known deposition technique to allow layers of polycrystalline semiconductor material.
    Several stacks "layer of polycrystalline semiconductor material - interface zone" could be made to form the region rich in CP traps.
    Subsequently, as illustrated in FIG. 6, the layer of polycrystalline semiconductor material 60 is planarized, for example by mechanochemical polishing (CMP for “Chemical Mechanical Planarization”). The hard mask layer 40 is also removed.
    The stages of formation of the integrated circuit are in fact carried out on the whole of a semiconductor wafer (wafer). These are so-called "full plate" operations
    Also, is it possible, before performing the planarization of the layer of polycrystalline semiconductor material 60 by mechanochemical polishing, to perform a partial etching of the layer 60 in the DI domain in order to remove the layer of semiconductor material polycrystalline 60 present in this area.
    This method makes it possible to avoid carrying out full-plate planarization over a very large surface at a later date, which can cause bowls in places.
    After removal of the hard mask layer 40, there may remain a step between the upper part of the semiconductor film 30 and the upper part of the region rich in CP traps. It is possible to leave the step as is or to perform a localized withdrawal of the step, preferably corresponding to the thickness of the hard mask layer 40.
    Then, as illustrated in FIG. 6, one proceeds to the production of ZIS insulating regions, for example shallow isolation trenches, or a local oxide (LOCOS for “LOCal Oxidation of Silicon” according to the usual term Anglosaxon), in the semiconductor film 30.
    Then, one proceeds in the conventional manner to the formation of non-radiofrequency components TRR for example, transistors in the domain D1, and also to the conventional formation of radiofrequency components CP, for example, of the inductors in the domain D2. These radio frequency components are in practice separated from the region rich in traps by a dielectric region RD, generally thick. When these components are for example produced at the first metallization level of the integrated circuit, the region RD is the region known to the skilled person under the term "PMD region" (PMD: "PreMetal Dielectric").
    Then, the manufacture of the integrated circuit IC is terminated by conventional conventional steps not shown here for the sake of simplification.
    As illustrated in FIG. 6, the integrated circuit IC here comprises the substrate 10 of the FD-SOI type, the first domain D1 and the second domain D2. The substrate contains a region rich in traps only in the second domain D2.
    The first domain D1 comprises a semiconductor film 30 on which are present non-radiofrequency components TRR.
    The second domain D2 comprises, in addition to the region rich in traps CP, radiofrequency components CR formed on the upper face of said region rich in traps CP. The region rich in traps CP is separated from the second part 12 of the carrier substrate 12 by the interface zone ZI.
    The invention is not limited to these modes of implementation but embraces all the variants. For example, although an SOI substrate has been described, the invention can be applied to a solid substrate comprising a region rich in traps located only in certain places.
    权利要求:
    Claims (14)
    [1" id="c-fr-0001]
    1. Integrated circuit (IC) comprising a substrate (1), at least a first domain (Dl), and at least a second domain (D2) distinct from said at least one first domain (Dl), in which the substrate (1) contains a region rich in traps (CP) only in said at least one second domain (D2).
    [2" id="c-fr-0002]
    2. Integrated circuit (IC) according to claim 1, in which said at least one first domain (Dl) contains at least one non-radio frequency component (TRR) and said at least one second domain (D2) contains at least one radio frequency component ( CR).
    [3" id="c-fr-0003]
    3. Integrated circuit (IC) according to claim 1 or 2, in which the substrate (1) is of the silicon on insulator type comprising in said at least one first domain (Dl), a semiconductor film (30), a first part of a carrier substrate and a buried insulating layer (20) located between said first part of the carrier substrate and the semiconductor film (30), and comprising in said second area (D2) a second part of the carrier substrate (12) surmounted by said region rich in traps (CP), the semiconductor film (30) and said buried insulating layer (20) not extending in said at least one second domain (D2).
    [4" id="c-fr-0004]
    4. Integrated circuit (IC) according to claim 3, in which the substrate is of the totally deserted silicon on insulator type, the semiconductor film (30) comprising a totally deserted semiconductor material.
    [5" id="c-fr-0005]
    5. Integrated circuit (IC) according to one of claims 3 or 4, wherein said trap-rich region (CP) comprises at least one stack comprising a layer of polycrystalline semiconductor material (60), and a zone of interface (ZI) located between an underlying part of the substrate and the layer of polycrystalline semiconductor material (60), said interface zone (ZI) having a structure distinct from the crystal structure of said layer of semiconductor material polycrystalline (60), and the crystal structure of the underlying part of the substrate.
    [6" id="c-fr-0006]
    6. Integrated circuit (IC) according to claim 5, wherein said at least one layer of polycrystalline semiconductor material (60) has a thickness of between 0.5 and 3 μm.
    [7" id="c-fr-0007]
    7. Integrated circuit (IC) according to claim 5 or 6 and one of claims 3 or 4, in which the underlying part of the substrate is said second part (12) of the carrier substrate (10).
    [8" id="c-fr-0008]
    8. Integrated circuit (IC) according to one of claims 3 to 6, wherein the carrier substrate (10) comprises a high resistivity substrate.
    [9" id="c-fr-0009]
    9. A method of producing an integrated circuit (IC) comprising producing a region rich in traps (CP) in only part of a substrate of the integrated circuit.
    [10" id="c-fr-0010]
    10. The method of claim 9, comprising an embodiment of a first domain (Dl) containing at least one non-radiofrequency component (TRR) and an embodiment of a second domain (D2) containing at least one radiofrequency component (CR) as well than the region rich in traps (CP).
    [11" id="c-fr-0011]
    11. The method of claim 9 or 10, comprising carrying out isolation zones (ZIS) in the substrate, carried out after the realization of the region rich in traps (CP).
    [12" id="c-fr-0012]
    12. Method according to one of claims 9 to 11, in which the substrate is of the silicon on insulator substrate type comprising a semiconductor film (30), a carrier substrate (10) and an insulating layer (20) buried between the carrier substrate (10) and the conductive film (30), and the production of the region rich in traps (CP) comprises:
    - An embodiment of a trench (TR) in said at least one second area (D2) extending as far as the carrier substrate (10);
    - a formation of at least one interface zone (ZI) on the internal wall of said trench (TR), said interface zone (ZI) having a crystal structure different from the carrier substrate (10);
    a formation of at least one layer of polycrystalline semiconductor material (60) on said at least one interface zone (ZI), the layer of polycrystalline semiconductor material (60) forming said region rich in traps (CP), having an upper surface located substantially in the same plane as the upper surface of the semiconductor film (30), and having a structure distinct from the crystal structure of the interface region (ZI).
    [13" id="c-fr-0013]
    13. The method of claim 12, wherein the substrate is of the silicon type completely deserted on insulator, the semiconductor film (30) comprising a semiconductor material totally
    10 deserted.
    [14" id="c-fr-0014]
    14. Method according to one of claims 12 or 13, wherein the carrier substrate (10) comprises a high resistivity substrate.
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    同族专利:
    公开号 | 公开日
    CN209592039U|2019-11-05|
    EP3531444A1|2019-08-28|
    US20210327834A1|2021-10-21|
    US11075177B2|2021-07-27|
    FR3078436B1|2020-03-20|
    CN110190064A|2019-08-30|
    US20190267335A1|2019-08-29|
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    法律状态:
    2019-01-23| PLFP| Fee payment|Year of fee payment: 2 |
    2019-08-30| PLSC| Publication of the preliminary search report|Effective date: 20190830 |
    2020-01-22| PLFP| Fee payment|Year of fee payment: 3 |
    2021-11-12| ST| Notification of lapse|Effective date: 20211005 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1851615|2018-02-23|
    FR1851615A|FR3078436B1|2018-02-23|2018-02-23|INTEGRATED CIRCUIT COMPRISING A SUBSTRATE EQUIPPED WITH A TRAP-RICH REGION, AND MANUFACTURING METHOD|FR1851615A| FR3078436B1|2018-02-23|2018-02-23|INTEGRATED CIRCUIT COMPRISING A SUBSTRATE EQUIPPED WITH A TRAP-RICH REGION, AND MANUFACTURING METHOD|
    EP19157369.0A| EP3531444A1|2018-02-23|2019-02-15|Integrated circuit including a substrate provided with a region rich in traps, and method for manufacturing same|
    US16/278,313| US11075177B2|2018-02-23|2019-02-18|Integrated circuit comprising a substrate equipped with a trap-rich region, and fabricating process|
    CN201910132573.2A| CN110190064A|2018-02-23|2019-02-22|Integrated circuit and manufacturing process including being equipped with the substrate of rich trap area|
    CN201920224028.1U| CN209592039U|2018-02-23|2019-02-22|Integrated circuit|
    US17/359,872| US20210327834A1|2018-02-23|2021-06-28|Integrated circuit comprising a substrate equipped with a trap-rich region, and fabricating process|
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